• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a mode detection circuit in a liquid crystal display device, which detects an input signal and automatically selects a mode corresponding thereto. The present invention provides a clock signal for detecting a vertical synchronization signal by inputting a main clock signal in an automatic mode selection circuit for detecting a vertical synchronization signal input to a liquid crystal display and selecting a DE / SYNC mode or a DE only mode. A clock signal generator; A vertical synchronous signal detector for inputting a clock signal applied from the clock signal generator to detect whether a vertical synchronous signal is input and generating a detection signal; A selection signal generator for inputting a detection signal output from the vertical synchronization signal detector to generate a mode selection signal; And a mode selection unit for inputting a mode selection signal generated from the selection signal generator to select one of a DE / SYNC mode signal and a DE only mode signal.
    公开号:KR19990056740A
    申请号:KR1019970076751
    申请日:1997-12-29
    公开日:1999-07-15
    发明作者:이순재
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Automatic Mode Detection Circuit of LCD
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic mode detection circuit of a liquid crystal display device, and more particularly, to an automatic mode detection circuit for detecting the presence of a vertical synchronization signal applied to a liquid crystal module and selecting a mode corresponding thereto.
    Currently, only notebook signal manufacturers enable the DE signal, which is the data enable signal, to the liquid crystal module, or the data enable signal DE + SYNC signal including the synchronization signal to the liquid crystal module.
    In the related art, there is an inconvenience of manually selecting a mode of a liquid crystal module using a jumper from the outside according to the mode of an input signal applied from a PC. In addition, since the controller does not operate even if the mode is manually changed by using a jumper from the outside, there is a problem that the circuit must be corrected in this case.
    Therefore, in order to respond to a PC manufacturer applying different types of signals to the liquid crystal module as a controller, a function for selecting a mode according to an input signal must be added to the controller.
    The present invention is to solve the problems of the prior art as described above, the automatic mode detection circuit of the liquid crystal display device that can automatically select one of the DE only mode or DE / VSYNC mode by detecting the presence of the vertical synchronization signal input The purpose is to provide.
    1 is a block diagram of an automatic mode detection circuit of a liquid crystal display device according to an embodiment of the present invention;
    2 is a detailed circuit diagram of an automatic mode detection circuit of a liquid crystal display device according to an embodiment of the present invention;
    3 is an operation waveform diagram in the DE / SYNC mode in which the vertical synchronization signal exists;
    4 is an operation waveform diagram in the DE only mode without the vertical synchronization signal,
    5A and 5B are views for explaining a DE only mode and a DE / SYNC mode;
    (Explanation of symbols for the main parts of the drawing)
    10: clock signal generation unit 20: vertical synchronous signal detection unit
    30: selection signal generator 40: mode selection unit
    11, 12, 22: 4-bit binary counter 21, 23, 32, 41: inverter
    31: D flip-flop 42, 43: multiplexer
    In order to achieve the above object of the present invention, the present invention is to provide a main clock signal in the automatic mode selection circuit for detecting the vertical synchronization signal input to the liquid crystal display device to select the DE / SYNC mode or DE only mode A clock signal generator for generating a clock signal for detecting the vertical synchronization signal; A vertical synchronous signal detector for inputting a clock signal applied from the clock signal generator to detect whether a vertical synchronous signal is input and generating a detection signal; A selection signal generator for inputting a detection signal output from the vertical synchronization signal detector to generate a mode selection signal; And a mode selection unit for inputting a mode selection signal generated from the selection signal generator to select one of a DE / SYNC mode signal and a DE only mode signal.
    According to an exemplary embodiment of the present invention, the clock signal generation unit may include: a first counter configured to apply an initial reset signal to a clear terminal and count a main clock signal applied as a clock signal to generate a 4-bit output; The initial reset signal is applied to a clock terminal and counts the highest output signal of the 4-bit output of the first counter applied as a clock signal to generate the lowest output signal of the 4-bit output signal as a clock signal for detecting a vertical synchronization signal. It is characterized by consisting of a second counter.
    According to an embodiment of the present invention, the vertical synchronous signal detector comprises: a first inverter for inputting and inverting a vertical synchronous signal; A clock signal loaded by the vertical synchronization signal inverted through the first inverter and output from the clock signal generator, and generating a pulse signal whenever a predetermined clock signal is applied from the clock signal generator; 3 counters; And a second inverter for inverting the output of the third counter and generating a detection signal indicating whether the vertical synchronization signal is input.
    According to an exemplary embodiment of the present invention, the selection signal generator includes a flip-flop to which a high power supply voltage is applied as an input signal and uses the output of the second inverter as a clock signal; And a third inverter for inverting the output of the flip-flop to generate a mode selection signal.
    According to an embodiment of the present invention, the mode selector comprises first and second multiplexers for selecting one of the DE mode signal and the DE / SYNC mode signal by the mode selection signal generated from the selection signal generator. do.
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    1 is a block diagram of an automatic mode detection circuit of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of FIG. 1.
    1 and 2, the automatic mode detection circuit of the present invention includes a clock signal generator 10 which inputs a main clock signal MCLK and generates a clock signal ICLK for detecting a vertical synchronization signal. do.
    The clock signal generator 10 is cleared by the initial reset signal FRST, and then generates a clock signal ICLK for detecting the presence of the vertical synchronization signal by counting the main clock signal MCLK. do.
    The clock signal generator 10 includes a 4-bit binary counter 11 to which an initial reset signal FRST is applied to a clear terminal CLR, and a main clock signal MCLK is applied to the clock signal CLK. The 4-bit binary counter 11 is composed of a 4-bit binary counter 12 of which the most significant output signal of the 4-bit output of the 4-bit binary counter 11 is applied as the clock signal CLK and the initial reset signal FRST is applied to the clear terminal CLR. The least significant bit output signal Q0 of the 4-bit binary counter 12 is generated as a clock signal ICLK for vertical synchronization signal detection.
    The automatic mode detecting circuit of the present invention inputs the clock signal ICLK applied from the clock signal generator 10 to detect the presence of the vertical synchronizing signal VSYNC to generate the vertical detection signal DCT. The signal detector 20 is included.
    The vertical synchronous signal detection unit 20 is an inverter 21 for inverting the vertical synchronous signal VSYNC and a vertical synchronous signal cleared by the initial reset signal FRST and inverted through the inverter 21. A 4-bit binary counter 22 which is loaded at the positive edge of VSYNC and inputs the output signal ICLK of the clock signal generator 10 as the clock signal CLK, and the output of the binary counter 22 An inverter 23 for inverting the RCO, and generates a detection signal DCT indicating whether or not a vertical synchronization signal is input whenever a predetermined output signal ICLK is applied from the clock signal generator 10. do.
    The automatic mode detection circuit of the present invention generates a mode selection signal DE_S for selecting one of the DE only mode signal and the DE / SYNC mode signal according to the detection signal DCT output from the vertical synchronous signal detection unit 20. It includes a selection signal generator 30 for.
    The selection signal generation unit 30 uses the detection signal DCT output from the vertical synchronization signal detection unit 20 as a clock signal, and is cleared by the initial reset signal FRST and is set to the input signal D high. The D flip-flop 31 to which the power supply voltage VCC in the state is applied and the inverter 32 inverting the output of the D flip-flop 31 to generate the mode selection signal DE_S.
    The automatic mode detection circuit of the present invention selects the mode selector 40 to select the DE / SYNC mode signal or the DE only mode signal according to the mode selection signal DE_S generated from the selection signal generator 30. Include.
    The mode selector 40 may include a DE only mode signal according to an inverter 41 for inverting the vertical synchronization signal VSYNC and a mode select signal DE_S generated from the select signal generator 30. It consists of multiplexers 42 and 43 for selecting one of the DE / VSYNC mode signals. When the vertical synchronization signal VSYNC is detected and the mode selection signal DE_S is low, the DE / VSYNC mode is selected to select the GSC_I signal. The vertical synchronization signal VSYNC inverted through the inverter 41 is applied to the internal signal generator (not shown) of the liquid crystal module, and the mode selection signal DE_S is not detected because the vertical synchronization signal VSYNC is not detected. If high, select DE only mode and apply DE only mode signal to the internal signal generator of LCD.
    The operation of the automatic mode detection circuit of the present invention having the above configuration will be described with reference to the waveform diagrams of Figs.
    First, the DE only mode and the DE / VSYNC mode will be described with reference to FIGS. 5A and 5B.
    In the DE only mode, as shown in FIG. 5A, the blank period BLK recognized as the vertical synchronization signal VSYNC is present in the data enable signal DE1 itself, so that the vertical synchronization signal (DE) is used only with the data enable signal DE. VSYNC) can be substituted. Therefore, in this case, even if the vertical synchronization signal VSYNC1 is not applied separately, the liquid crystal module can be operated because the data enable signal DE1 is a complete signal.
    In the DE / VSYNC mode, as shown in FIG. 5B, unlike the data enable signal DE1 of FIG. 5A, a blank section capable of recognizing a vertical synchronization signal does not exist in the data enable signal DE2. In order to drive the module, both the data enable signal DE2 and the vertical synchronization signal VSYNC2 are required.
    In the present invention, as described above, when the vertical synchronization signal VSYNC is detected by detecting the presence of the vertical synchronization signal, the DE / VSYNC mode signal is selected to select the DE / VSYNC mode signal, and the vertical synchronization signal VSYNC ) Is not applied, it recognizes as DE only mode and selects DE only mode signal.
    Next, an operation of selecting one of the DE / VSYNC mode signal and the DE only mode signal by detecting the mode of the input signal will be described with reference to FIGS. 3 and 4.
    The clock signal generator 10 counts the main clock signal MCLK applied to the clock signal CLK by the counters 11 and 12 being reset by the initial reset signal FRST. At this time, when 40 MHz is applied as the main clock signal MCLK, the period of the main clock signal MCLK is 25 ns.
    Among the 4-bit outputs of the counter 11 whose main clock signal MCLK is the clock signal, the most significant output signal Q3 is applied as the clock signal of the counter 12 at the rear stage, and the 4-bit output of the counter 12 is output. The lowest output signal Q0 is output as a clock signal ICLK for vertical synchronization signal detection. At this time, the clock signal ICLK output from the counter 12 has a period of 800 ns.
    The clock signal ICLK generated from the clock signal generator 10 is applied to the vertical synchronization signal detector 20, and the counter 22 is positive of the vertical synchronization signal VSYNC inverted through the inverter 21. The clock signal ICLK, which is loaded at the edge and generated from the clock signal generator 10, is counted.
    As shown in FIG. 4, when the vertical synchronizing signal VSYNC is not input, the vertical synchronizing signal VSYNC is kept in a high state, and the output of the inverter 21 becomes low so that the counter 22 Since the counter 22 is applied to the load terminal LOAD, the counter 22 may not count the clock signal ICLK applied from the clock signal generator 10 applied to the clock terminal.
    Accordingly, the vertical synchronization signal detector 20 outputs the detection signal DCT in the low state to the selection signal generator 30 through the inverter 23. The selection signal generator 30 generates a mode detection signal DE_S in a high state through the inverter 32 and is applied to the mode selector 40.
    The mode selector 40 selects the DE only mode signal through the multiplexers 41 and 42 by the mode select signal DE_S of the high state generated from the select signal generator 30.
    However, when the vertical synchronizing signal VSYNC is input, as shown in FIG. 3, the vertical synchronizing signal VSYNC has a low state section, and in the low state section, the output of the inverter 21 is inverted to a high state. The counter 22 is loaded. Accordingly, the counter 22 counts the clock signal ICLK of the clock signal generator 10 applied to the clock terminal.
    Accordingly, the counter 22 generates a pulse signal at regular intervals, and this signal is inverted through the inverter 23 to generate the detection signal DCT. At this time, the counter 22 generates a pulse signal whenever the 16th clock signal ICLK is applied from the clock signal generator 10, and accordingly, the detection signal DCT is generated.
    Since the detection signal DCT is applied as a clock signal of the D flip-flop 31 of the selection signal generator 30, the selection signal generator 30 is first generated when the detection signal DCT is first changed from a low state to a high state. The output of flip flop 31 of becomes high. Therefore, the inverter 32 generating the mode selection signal DE_S by inverting the output of the flip-flop 31 generates the output signal DE_S in the low state as shown in FIG. 3.
    The mode selector 40 inputs the mode select signal DE_S in the low state to the mode selector 40, selects the DE / SYNC mode according to the mode select signal DE_S in the low state, and selects the DE / SYNC mode signal. (GSC_I, VSYNC) is output to the internal signal generator. At this time, the signal GSC_I is a gate shift clock signal and is a signal generated from the controller to drive the gate driver of the liquid crystal module.
    The mode selector 40 selects the DE only mode signal through the multiplexers 41 and 42 by the mode select signal DE_S of the high state generated from the select signal generator 30.
    In the present invention, when the clock signal ICK is applied from the clock signal generation unit 10 for the 16th time, the mode selection signal DE_S in the low state is generated, so that the influence of noise can be eliminated.
    According to the present invention as described above, the present invention can detect whether the vertical synchronization signal input or not, and automatically selects either the DE only mode or the DE / SYNC mode according to the detection result.
    Therefore, it is simple to select a mode simply without having to change the mode by using a jumper manually.
    In addition, there is an advantage that it is possible to correspond with one controller for different modes.
    In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] In the automatic mode selection circuit for detecting the vertical synchronization signal input to the liquid crystal display element to select the DE / SYNC mode or DE only mode,
    A clock signal generator for inputting a main clock signal to generate a clock signal for detecting a vertical synchronization signal;
    A vertical synchronous signal detector for inputting a clock signal applied from the clock signal generator to detect whether a vertical synchronous signal is input and generating a detection signal;
    A selection signal generator for inputting a detection signal output from the vertical synchronization signal detector to generate a mode selection signal;
    And a mode selection unit for inputting a mode selection signal generated from the selection signal generator to select one of a DE / SYNC mode signal and a DE only mode signal.
    [2" claim-type="Currently amended] The method of claim 1, wherein the clock signal generation unit
    A first counter applied with an initial reset signal to the clear terminal, and counting a main clock signal applied as a clock signal to generate a 4-bit output;
    The initial reset signal is applied to a clock terminal and counts the highest output signal of the 4-bit output of the first counter applied as a clock signal to generate the lowest output signal of the 4-bit output signal as a clock signal for detecting a vertical synchronization signal. An automatic mode detection circuit of a liquid crystal display element, comprising a second counter.
    [3" claim-type="Currently amended] The method of claim 1, wherein the vertical synchronization signal detector
    A first inverter for inputting and inverting the vertical synchronization signal;
    A clock signal loaded by the vertical synchronization signal inverted through the first inverter and output from the clock signal generator, and generating a pulse signal whenever a predetermined clock signal is applied from the clock signal generator; 3 counters;
    And a second inverter for inverting the output of the third counter and generating a detection signal indicating whether or not a vertical synchronization signal is input.
    [4" claim-type="Currently amended] The method of claim 1, wherein the selection signal generator
    A flip-flop is applied with a high power supply voltage as an input signal and uses the output of the second inverter as a clock signal;
    And a third inverter for inverting the output of the flip-flop to generate a mode selection signal.
    [5" claim-type="Currently amended] The method of claim 1, wherein the mode selection unit
    And first and second multiplexers for selecting one of the DE mode signal and the DE / SYNC mode signal by the mode selection signal generated from the selection signal generator.
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    同族专利:
    公开号 | 公开日
    KR100429394B1|2004-06-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-12-29|Application filed by 김영환, 현대전자산업 주식회사
    1997-12-29|Priority to KR1019970076751A
    1998-12-11|Priority claimed from US09/209,718
    1999-07-15|Publication of KR19990056740A
    2004-06-16|Application granted
    2004-06-16|Publication of KR100429394B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970076751A|KR100429394B1|1997-12-29|1997-12-29|Automatic mode detection circuit of lcd|
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